hanbit hm d4m36m3eg url:w ww.hbe.co.kr hanbit electronics co.,ltd. rev.1.0 (august.2002) 1 general description the hmd4m36m3e is a 4m x 36 bit dynamic ram high - density memory module. the module consists of two cmos 4m x 16 bit drams in 50 - pin tsop packages and one cmos 4m x 4bit quad cas dram in 28pin soj package mounted on a 72 - pin. a 0. 1 or 0.22uf decoupling capacitor is mounted on the printed circuit board for each dram components. the module is a single in - line memory module with edge connections and is intended for mounting in to 72 - pin edge connector sockets. all module components ma y be powered from a single 5v dc power supply. all inputs and outputs are ttl - compatible. features w part identification hmd4m36m3e ---- 4k cycles/64ms ref, solder hmd4m36 m3eg - 4k cycles/64ms ref, gold w access times : 50, 60ns w high - density 16mbyte design w single +5v 0.5v power supply w jedec standard pinout w edo mode operation w ttl compatible inputs and outputs w fr4 - pcb design option s marking w timing 50ns access - 5 60 n s access - 6 w packages 72 - pin simm m presence detect pins pin 50ns 60ns pd1 vss vss pd2 nc nc pd3 vss nc pd4 vss nc performance range speed trac tcac trc thpc 5 50ns 13ns 90ns 26ns 6 60ns 15ns 110ns 30ns pin symbol pin symbol pin symbol 1 vss 25 dq2 4 49 dq 9 2 dq0 26 dq7 50 dq2 7 3 dq1 8 27 dq2 5 51 dq 10 4 dq1 28 a7 52 dq2 8 5 dq1 9 2 9 a11 53 dq1 1 6 dq2 30 vcc 54 dq2 9 7 dq 20 31 a8 55 dq1 2 8 dq3 32 a9 56 dq 30 9 dq 21 33 nc 57 dq1 3 10 vcc 34 nc 58 dq 31 11 nc 35 dq26 59 vcc 12 a0 36 dq8 60 dq 32 13 a1 37 dq17 61 dq1 4 14 a2 38 dq35 62 dq 33 15 a3 39 vss 63 dq1 5 16 a4 40 /cas0 64 dq 3 4 17 a5 41 /cas2 65 dq1 6 18 a6 42 /cas3 66 nc 19 a10 43 /cas1 67 pd1 20 dq4 44 /ras0 68 pd2 21 dq2 2 45 nc 69 pd3 22 dq5 46 nc 70 pd4 23 dq2 3 47 /w e 71 nc 24 dq6 48 nc 72 vss 16mbyte(4mx36) 72 - pin simm edo wi th parity mode, 4k ref. 5v part no. hm d4m36m3e, HMD4M36M3EG pin assignment
hanbit hm d4m36m3eg url:w ww.hbe.co.kr hanbit electronics co.,ltd. rev.1.0 (august.2002) 2 functional block dia gram vss 0.1uf or 0.22uf capacitor for each dram to all drams /ras0 /cas0 /cas1 /cas2 /cas3 /w e a0 - a11 dq0 - dq7 dq9 - dq16 dq8 dq17 dq26 dq35 dq18 - dq25 dq27 - dq34 /ras /lcas /ucas /oe /w a0 - a11 u 1 /ras /cas0 dq0 /cas1 dq1 /cas2 dq2 /cas3 dq3 /w a0 - a11 u 2 /ras /lcas /ucas /oe w a0 - a11 u 3 vcc dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq16 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15
hanbit hm d4m36m3eg url:w ww.hbe.co.kr hanbit electronics co.,ltd. rev.1.0 (august.2002) 3 absolute maximum rat ings parameter symbol rating voltage on any pin relative to vss v in ,out - 1v to 7.0v voltage on vcc supply relative to vss vcc - 1v to 7.0v po wer dissipation p d 3 w storage temperature t stg - 55 o c to 150 o c short circuit output current i os 50ma w permanent device damage may occur if " absolute maximum ratings" are exceeded. functional operation should be restricted to the conditions as detail ed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended dc opera ting conditions ( voltage reference to v ss , t a =0 to 70 o c ) parameter symbol min typ . max unit supply voltage vcc 4.5 5.0 5.5 v ground vss 0 0 0 v input high voltage v ih 2.4 - vcc+1 v input low voltage v il - 1.0 - 0.8 v dc and operating cha racteristics symbol speed min max units - 5 - 990 ma i cc1 - 6 - 900 ma i cc2 - 18 ma - 5 - 990 ma i cc3 - 6 - 900 ma - 5 - 990 ma i cc4 - 6 - 900 ma i cc5 - 9 ma - 5 - 990 ma i cc6 - 6 - 900 ma i l(l) - 40 45 m a i o(l) - 5 5 m a v oh 2.4 - v v ol - 0.4 v i cc1 : operating current * (/ras , /cas , address cycling @t rc =min.) i cc2 : stan dby current ( /ras=/cas=v ih ) i cc3 : /ras only refresh current * ( /cas=v ih , /ras, address cycling @t rc =min )
hanbit hm d4m36m3eg url:w ww.hbe.co.kr hanbit electronics co.,ltd. rev.1.0 (august.2002) 4 i cc4 : fast page mode current * (/ras=v il , /cas, address cycling @t pc =min ) i cc5 : standby current (/ras=/cas=vcc - 0.2v ) i cc6 : /cas - before - /ras r efresh current * (/ras and /cas cycling @t rc =min ) i il : input leakage current (any input 0v v in 6.5v, all other pins not under test = 0v) i ol : output leakage current (data out is disabled, 0v v out 5.5v v oh : output high voltage level (i oh = - 5ma ) v ol : output low voltage level (i ol = 4.2ma ) * note : i cc1 , i cc3 , i cc4 and i cc6 are dependent on output loading and cycle rates. specified values are obtained with the output open. i cc is specified as an average current. in i cc1 and i cc3 , a ddress cad be changed maximum once while /ras=v il . in i cc4 , address can be changed maximum once within one page mode cycle. capacitance ( t a =25 o c, vcc = 5v, f = 1mz ) description symbol min max units input capacitance (a0 - a10) c in1 - 65 pf inp ut capacitance (/w) c in2 - 80 pf input capacitance (/ras0) c in3 - 50 pf input capacitance (/cas0 - /cas3) c in4 - 40 pf input/output capacitance (dq0 - 31) c dq1 - 20 pf ac characteristics ( 0 o c t a 70 o c , vcc = 5v 10%, see notes 1,2.) - 5 - 6 standard operat ion symbol min max min max unit random read or write cycle time t rc 90 110 ns access time from ras t rac 50 60 ns access time from cas t cac 13 15 ns access time from column address t aa 25 30 ns cas to output in low - z t clz 3 3 ns output buffer turn - off delay t off 3 13 3 15 ns transition time (rise and fall) t t 2 50 2 50 ns /ras precharge time t rp 30 40 ns /ras pulse width t ras 50 10k 60 10k ns /ras hold time t rsh 13 15 ns /cas hold time t csh 38 45 ns /cas pulse width t cas 8 10k 10 10k ns /ras to /cas delay time t rcd 20 37 20 45 ns /ras to column address delay time t rad 15 25 15 30 ns /cas to /ras precharge time t crp 5 5 ns row address set - up time t asr 0 0 ns row address hold time t rah 10 10 ns
hanbit hm d4m36m3eg url:w ww.hbe.co.kr hanbit electronics co.,ltd. rev.1.0 (august.2002) 5 column address set - up time t asc 0 0 ns column address hold time t cah 8 10 ns column address to /ras lead time t ral 25 30 ns read command set - up time t rcs 0 0 ns read command hold referenced to /cas t rch 0 0 ns read command hold referenced to /ras t rrh 0 0 ns write command hold time t wch 10 10 ns write command hold referenced to /ras t wcr 50 50 ns write command pulse width t wp 10 10 ns write command to /ras lead time t rwl 13 15 ns write command to /cas lead time t cwl 8 10 ns data - in set - up time t ds 0 0 ns data - in hold time t dh 8 10 ns data - in hold referenced to /ras t dhr 50 50 ns refresh period t ref 64 64 ns write command set - up time t wcs 0 0 ns /cas setup time (c - b - r refresh) t csr 5 5 ns /cas hold time (c - b - r refresh) t chr 10 10 ns /ras precharge to /cas hold time t rpc 5 5 ns access time from /cas precharge t cpa 30 35 ns fast page mode cycle time t pc 40 40 ns /cas precharge time (fast page) t cp 8 10 ns /ras pulse width (fast page ) t rasp 50 200k 60 200k n s /w to /ras precharge time (c - b - r refresh) t wrp 10 10 ns /w to /ras hold time (c - b - r refresh) t wrh 10 10 ns /cas precharge(c - b - r counter test) t cpt 20 20 ns notes 1. an initial pause of 200 m s is required after power - up followed by any 8 /ras - only o r /cas - before - /ras refresh cycles before proper device operation is achieved. 2. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih(min) and v il(max) and are assumed to be 5ns for all inputs. 3. measured with a load equivalent to 2ttl loads and 100pf 4. operation within the t rcd(max) limit insures that t rac(max) can be met. t rcd(max) is specified as a reference point only. if t rcd is greater than the specified t rcd(max) limit, then access tim e is controlled exclusively by t cac . 5. assumes that t rcd 3 t rcd(max) 6. t ar , t wcr , t dhr are referenced to t rad(max) 7.this parameter defines the time at which the output achieves the open circuit condition and is not referenced to v oh or v ol . 8. t wcs , t rwd , t cwd and t awd are non restrictive operating parameter. they are included in the data sheet as electrical characteristic only. if t wcs 3 twcs(min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. 9. either t rch or t rrh must be satisfied for a read cycle. 10. these parameters are referenced to the /cas leading edge in early write cycles and to the /w leading edge in read - write cycles. 11. operation within the t rad(max) limit insures t hat t rac(max) can be met. t rad(max) is specified as a reference point only. if t rad is greater than the specified t rad(max) limit. then access time is controlled by t aa .
hanbit hm d4m36m3eg url:w ww.hbe.co.kr hanbit electronics co.,ltd. rev.1.0 (august.2002) 6 0.25 mm max min 2.54 mm 1.27 mm gold : 1.04 0. 10 mm solder:0.914 0.10mm packaging informatio n o r dering information part number density or g. package vcc speed HMD4M36M3EG - 5 16 mbyte 4 mx 3 6 bit 72 pin - simm 5.0v 5 0ns HMD4M36M3EG - 6 16 mbyte 4mx 3 6 bit 72 pin - simm 5.0v 60ns max 5.08 mm 1.29 0.08 mm 10.16 mm 107.95 mm 95.25 mm 6.35 m m r1.57 10 mm 6.35 mm 2.03 mm 18.52 mm 6.35 mm 101.19 mm r1.57 mm 3.18 0.51 3.38 mm
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